1. Field of the Invention
The present invention relates to dynamic RAMs that require periodic refresh operations of the memory cells thereof. More particularly, the present invention relates to a technique for internally and automatically performing the refresh operations without requiring any refresh commands from the exterior.
2. Description of the Related Art
Dynamic RAMs (hereinafter referred to as DRAMs) are suitable for a high integration because their memory cells can be formed small. The DRAMs, however, require refresh operations for retaining data stored in the memory cells. The refresh operations must be periodically performed with respect to all the memory cells. When a refresh command occurs, a refresh operation must be given priority over a read or write operation.
For example, in the system on which a DRAM is mounted, a memory controller for controlling the DRAM supplies a refresh command to the DRAM prior to a read or write command when the refresh command occurs from a refresh timer of the memory controller.
On the other hand, SRAMs, unlike DRAMs, require no refresh operations. The SRAMs, however, have such a disadvantage that their memory capacities are small as compared with DRAMs because the number of the elements constituting each memory cell of the SRAMs is large as compared with the DRAMs.
The conventional DRAMs had a drawback that the control of them was complicated as compared with the SRAMs because the memory controllers of the DRAMs had to control the refresh operations as well. The conventional DRAMs also had a drawback that their data transmission rates were low as compared with the SRAMs because the read and write operations could not be performed during the refresh operations.
On the other hand, the SRAMs had, in addition to the aforementioned difficulty of providing large capacities, a drawback that the chip costs of the SRAMs are very high as compared with the DRAMs because the memory cells of the SRAMs are large in size.
It is an object of the present invention to provide semiconductor memories having both large capacity of DRAMs and high usability of SRAMs.
It is another object of the present invention to provide semiconductor memories that respond to externally supplied requests for read operation at high speed, and that have a high data-transmission rate.
According to one of the aspects of the semiconductor memory of the present invention, a plurality of memory blocks are allocated the same address spaces so as to write the same data therein, and are operable independently of one another. A refresh generator generates a refresh command to refresh the memory cells. A refresh control unit selects one of the memory blocks as a refresh block that performs a refresh operation in response to the refresh command. A read control unit selects one of the memory blocks other than the refresh block as a read block that performs a read operation in response to a read command. When a new read command is supplied during the read operation performed by the read block, the read control unit also selects another one of the memory blocks which is in an idle state other than the refresh block as a read block that performs a read operation in response to the new read command.
The plurality of memory blocks performs the read operations at different timings so that the read operations performed overlap one another. The overlapping operations of the memory blocks allow the semiconductor memory to receive read commands at intervals each of which is shorter than the internal read cycle time required for the memory blocks to perform a single read operation. That is, read commands supplied from the exterior can be responded to at high speed. As a result, the data transmission rate during read operation can be improved. Especially, in a semiconductor memory that internally generates refresh requests for performing refresh operations, the read operations can be performed at high speed.
A refresh operation is performed only in a refresh block, and a read operation is performed only in a read block. Therefore, the read operation can be prevented from being interfered with by the refresh operation.
According to another aspect of the semiconductor memory of the present invention, the refresh control unit includes a refresh block counter that performs a count operation in response to the refresh command and outputs a refresh block signal indicative of the refresh block. The read control unit includes a read block counter that performs the count operation in response to the read command and outputs a read block signal indicative of the read block. One of the memory blocks that receives the refresh block signal starts, as the refresh block, the refresh operation in response to the refresh command. Another one of the memory blocks that receives the read block signal starts, as the read block, a read operation in response to the read command. Using the counters that operate in response to commands when selecting refresh and read blocks allows simple circuits to select memory blocks in which refresh and read operations are performed.
According to another aspect of the semiconductor memory of the present invention, the read block counter updates a counter value to differentiate the read and refresh block signals from each other when the read block signal coincides with the refresh block signal by performing the count operation. Therefore, it can be prevented that a single memory block becomes both read and refresh blocks. As a result, the read operation can be prevented from being delayed due to the refresh operation. Additionally, malfunction of the memory blocks can be prevented.
According to another aspect of the semiconductor memory of the present invention, the update direction of the read block counter is opposite to the update direction of the refresh block counter. Therefore, one of the counter values can be prevented from following the other counter value, and malfunction of the memory blocks can be prevented.
According to another aspect of the semiconductor memory of the present invention, the number of the memory blocks is one more than the maximum number of the read commands that can be supplied during an internal read cycle time necessary for the memory blocks to perform a single read operation. Therefore, even when read commands are supplied successively, there always exists one memory block that is in a standby state (idle state). Accordingly, the read operations can be prevented from being delayed due to the refresh operation, and the data transmission rate during read operation can be improved.
According to another aspect of the semiconductor memory of the present invention, a write control circuit performs, in response to a write command, a write operation to write the same data into all of the memory blocks. Therefore, the read operation responsive to a read command can be performed in any of the memory blocks. Since a read operation can be started quickly in response to a read command, the data transmission rate during read operation can be improved.
According to another aspect of the semiconductor memory of the present invention, an arbiter sequentially performs operations according to write and refresh commands in the order of accepting the commands when the commands conflict with each other in the refresh block. Therefore, malfunction of the memory blocks can be prevented.
According to another aspect of the semiconductor memory of the present invention, the arbiter receives the write command in synchronization with one of rising and falling edges of the clock signal, and receives the refresh command in synchronization with the other one of the rising and falling edges of the clock signal. Since the reception of the write command and that of the refresh command are displaced by a half clock or more, the control circuit for deciding the priority order of the commands can be easily formed.
According to another aspect of the semiconductor memory of the present invention, when receiving the write command during the refresh operation, the write control circuit starts the write operation after a completion of the refresh operation in the refresh block, and starts the write operation in synchronization with the write command in the memory blocks other than the refresh block. Performing the write operations in synchronization with the write command in the memory blocks that are in idle states allows the memory operation responsive to a command supplied thereafter to be started earlier. Especially, since the read operation responsive to a read command can be started earlier, the data transmission rate during read operation can be improved.
According to another aspect of the semiconductor memory of the present invention, the edge of a clock signal at which a command receiving circuit receives read and write commands is different from the edge of a clock signal at which the refresh generator outputs a refresh command. The read and write commands from the exterior and the internally generated refresh command are supplied to internal circuits, always being displaced by a half clock or more. Thus, the control of deciding priority order of the command can be easily performed.
According to another aspect of the semiconductor memory of the present invention, the external read cycle time that is the minimum supply interval between the read commands is set as being shorter than the external write cycle time that is the minimum supply interval between write commands. Therefore, the external read cycle time can be optimally set in accordance with the circuits that operate during the read operations, so that the data transmission rate during read operation can be improved.
According to another aspect of the semiconductor memory of the present invention, the external write cycle time that is the minimum supply interval between write commands is supplied is set as being longer than the internal write cycle time that is the actual write operation time of the memory blocks. Therefore, when a refresh request occurs, a refresh operation can be performed between write operations. For example, n write operations and one of the refresh operation can be performed during a time period of n successive external write cycles. As a result, the refresh operation can be performed without being externally recognized.